FIG. 1 illustrates a schematic drawing of a prior art dynamic random access memory (DRAM) redundancy scheme which includes each memory block, labeled MB with an identifying subscript, and a plurality of redundant blocks of memory, RB, each associated with a memory block and carrying the same subscript. Each redundant block of memory RB and its associated memory block MB share bit lines (each bit line represent as BL). A plurality of sense amplifiers is also shown in FIG. 1 with each sense amplifier S/A (hereinafter referred to as sense amp) lying adjacent to and carrying the sam subscript as its associated memory block. Redundant blocks of memory serve to provide alternate memory service. For instance, if word line WL.sub.1 or a memory cell along word line WL.sub.1 in memory block MB.sub.1 is defective, word line WL.sub.1R in redundant memory block RB.sub.1 is used along with its row (illustrated as verticle columns) of memory cells (each asterisk representing a memory cell).